From the Wires
Cadence Delivers Design and Analysis Flow Enhancements for TSMC InFO and CoWoS® 3D Packaging Technologies
By: PR Newswire
Sep. 13, 2017 10:46 AM
SAN JOSE, Calif., Sept. 13, 2017 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced new capabilities that complete its holistic, integrated design flow for TSMC's advanced wafer-level Integrated Fan-Out (InFO) packaging technology. Additionally, Cadence has unveiled enhancements for TSMC's chip-on-wafer-on-substrate (CoWoS) advanced packaging technology. The complete InFO flow and enhanced CoWoS design methodologies enable design teams to efficiently complete the development process, from planning to analysis across multiple dies.
For more information on the completed TSMC InFO design flow and TSMC CoWoS reference flow, visit www.cadence.com/go/tsmcinfocowos.
Completed InFO Design Flow
The Cadence® tools that have been enhanced to complete the TSMC InFO flow include the Quantus™ QRC Extraction Solution, Physical Verification System (PVS), and the Voltus™ Sigrity™ Package Analysis solution. Additional tools in the flow include OrbitIO™ Interconnect Designer, System-in-Package (SiP) Layout, Sigrity XtractIM™ technology, Tempus™ Timing Signoff Solution, Sigrity PowerDC™ technology and Sigrity PowerSI® 3D-EM Extraction Option. With the completion of the flow, system-on-chip (SoC) designers can now:
CoWoS Reference Flow Enhancements
Cadence has also developed enhancements to the TSMC CoWoS reference flow. The new capabilities within the CoWoS refence flow enable designers to perform:
"We see a strong demand from both mobile and high-performance computing customers wanting to quickly deploy systems based on TSMC's advanced packaging technologies," said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence. "Through our close working relationship with TSMC, we have completed TSMC InFO design flow and enhanced TSMC CoWoS reference flow, enabling our mutual customers to further shorten design and verification cycle times so they can get to market faster."
"The Cadence solution for InFO technology enables our customers to deliver designs with increased bandwidth within small form factors," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "With these enhancements, the integrated full-flow addresses the market need for faster design and verification cycles. Additionally, the new capabilities added to the Cadence solution for CoWoS supports our customers who want to utilize this holistic reference flow for advanced packaging projects."
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company's System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at cadence.com.
© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc.
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SOURCE Cadence Design Systems, Inc.
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